27min read time (3500 words)
This Versal™ Adaptive SoC engineer-to-engineer designer’s journey explores step-by-step how Mercury's engineering team used Versal for a single test application. It is intended to assist other development teams as they adopt Versal design. Ever-increasing data volumes, rising computation demands and real-time performance expectations can no longer be satisfied by traditional solutions. With the introduction of Versal technology, AMD has enabled an innovative approach for the next era of specialized computing. This highly dense, next-generation chip solution combines multiple types of processing elements to form a whole new category of dramatically faster devices that step beyond the current CPU/GPU/FPGA paradigm. Utilizing this technology, we can now solve the most advanced radar, cognitive EW and AI challenges — all on a single board. Optimized to solve the most advanced radar, and cognitive EW and AI challenges.
Read this white paper to learn:
- Processing challeges solved by Versal
- Programming AIE processors
- Testing AIE using a single beamforming Kernel
- Overcoming AIE C++ code obstacles
- MATLAB simulation results
- Methods to improve design and trade-offs for AIE kernels
- Results, parameters and findings
- Multi-kernal architecture
- Design considerations for engineers using Versal
